# -*- mode:python -*-

# Copyright (c) 2006 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Steve Reinhardt

Import('*')

#################################################################
#
# Generate StaticInst execute() method signatures.
#
# There must be one signature for each CPU model compiled in.
# Since the set of compiled-in models is flexible, we generate a
# header containing the appropriate set of signatures on the fly.
#
#################################################################

# CPU model-specific data is contained in cpu_models.py
# Convert to SCons File node to get path handling
models_db = File('cpu_models.py')
# slurp in contents of file
execfile(models_db.srcnode().abspath)


# Template for execute() signature.
exec_sig_template = '''
virtual Fault execute(%(type)s *xc, Trace::InstRecord *traceData) const = 0;
virtual Fault eaComp(%(type)s *xc, Trace::InstRecord *traceData) const
{ panic("eaComp not defined!"); M5_DUMMY_RETURN };
virtual Fault initiateAcc(%(type)s *xc, Trace::InstRecord *traceData) const
{ panic("initiateAcc not defined!"); M5_DUMMY_RETURN };
virtual Fault completeAcc(Packet *pkt, %(type)s *xc,
                          Trace::InstRecord *traceData) const
{ panic("completeAcc not defined!"); M5_DUMMY_RETURN };
'''

mem_ini_sig_template = '''
virtual Fault eaComp(%(type)s *xc, Trace::InstRecord *traceData) const
{ panic("eaComp not defined!"); M5_DUMMY_RETURN };
virtual Fault initiateAcc(%s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); M5_DUMMY_RETURN };
'''

mem_comp_sig_template = '''
virtual Fault completeAcc(uint8_t *data, %s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); return NoFault; M5_DUMMY_RETURN };
'''

# Dec. 2009, Gou Pengfei
# Template for Edge execute() signature
edge_exec_sig_template = '''
virtual Fault execute(%(type)s *xc, Trace::EdgeInstRecord *traceData) const = 0;
virtual Fault eaComp(%(type)s *xc, Trace::EdgeInstRecord *traceData) const
{ panic("eaComp not defined!"); M5_DUMMY_RETURN };
virtual Fault initiateAcc(%(type)s *xc, Trace::EdgeInstRecord *traceData) const
{ panic("initiateAcc not defined!"); M5_DUMMY_RETURN };
virtual Fault completeAcc(Packet *pkt, %(type)s *xc,
                          Trace::EdgeInstRecord *traceData) const
{ panic("completeAcc not defined!"); M5_DUMMY_RETURN };
'''

edge_mem_ini_sig_template = '''
virtual Fault eaComp(%(type)s *xc, Trace::InstRecord *traceData) const
{ panic("eaComp not defined!"); M5_DUMMY_RETURN };
virtual Fault initiateAcc(%s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); M5_DUMMY_RETURN };
'''

edge_mem_comp_sig_template = '''
virtual Fault completeAcc(uint8_t *data, %s *xc, Trace::EdgeInstRecord *traceData)  const { panic("Not defined!"); return NoFault; M5_DUMMY_RETURN };
'''

# Generate a temporary CPU list, including the CheckerCPU if
# it's enabled.  This isn't used for anything else other than StaticInst
# headers.
temp_cpu_list = env['CPU_MODELS'][:]

if env['USE_CHECKER']:
    temp_cpu_list.append('CheckerCPU')
    SimObject('CheckerCPU.py')

# Generate header.
def gen_cpu_exec_signatures(target, source, env):
    f = open(str(target[0]), 'w')
    print >> f, '''
#ifndef __CPU_STATIC_INST_EXEC_SIGS_HH__
#define __CPU_STATIC_INST_EXEC_SIGS_HH__
'''    
    #
    # Dec. 2009, Gou Pengfei
    #
    if 'SimpleEdgeCPU' or 'DistributedEdgeCPU' or 'AtomicEdgeCPU' in temp_cpu_list:
        for cpu in temp_cpu_list:
            xc_type = CpuModel.dict[cpu].strings['CPU_exec_context']
            print >> f, edge_exec_sig_template % { 'type' : xc_type }
    else:
        for cpu in temp_cpu_list:
            xc_type = CpuModel.dict[cpu].strings['CPU_exec_context']
            print >> f, exec_sig_template % { 'type' : xc_type }
    print >> f, '''
#endif  // __CPU_STATIC_INST_EXEC_SIGS_HH__
'''

# Generate string that gets printed when header is rebuilt
def gen_sigs_string(target, source, env):
    return "Generating static_inst_exec_sigs.hh: " \
           + ', '.join(temp_cpu_list)

# Add command to generate header to environment.
env.Command('static_inst_exec_sigs.hh', models_db,
            Action(gen_cpu_exec_signatures, gen_sigs_string,
                   varlist = temp_cpu_list))

env.Depends('static_inst_exec_sigs.hh', Value(env['USE_CHECKER']))
env.Depends('static_inst_exec_sigs.hh', Value(env['CPU_MODELS']))

# List of suppported CPUs by the Checker.  Errors out if USE_CHECKER=True
# and one of these are not being used.
CheckerSupportedCPUList = ['O3CPU', 'OzoneCPU']

SimObject('BaseCPU.py')
SimObject('FuncUnit.py')
SimObject('ExeTracer.py')
SimObject('IntelTrace.py')
SimObject('NativeTrace.py')

Source('activity.cc')
Source('base.cc')
Source('cpuevent.cc')
Source('exetrace.cc')
Source('func_unit.cc')
Source('inteltrace.cc')
Source('nativetrace.cc')
Source('pc_event.cc')
Source('quiesce_event.cc')
Source('static_inst.cc')
Source('simple_thread.cc')
Source('thread_context.cc')
Source('thread_state.cc')

if env['FULL_SYSTEM']:
    SimObject('IntrControl.py')

    Source('intr_control.cc')
    Source('profile.cc')

    if env['TARGET_ISA'] == 'sparc':
        SimObject('LegionTrace.py')
        Source('legiontrace.cc')

if env['USE_CHECKER']:
    Source('checker/cpu.cc')
    TraceFlag('Checker')
    checker_supports = False
    for i in CheckerSupportedCPUList:
        if i in env['CPU_MODELS']:
            checker_supports = True
    if not checker_supports:
        print "Checker only supports CPU models",
        for i in CheckerSupportedCPUList:
            print i,
        print ", please set USE_CHECKER=False or use one of those CPU models"
        Exit(1)

TraceFlag('Activity')
TraceFlag('Commit')
TraceFlag('Context')
TraceFlag('Decode')
TraceFlag('DynInst')
TraceFlag('ExecEnable')
TraceFlag('ExecCPSeq')
TraceFlag('ExecEffAddr')
TraceFlag('ExecFaulting', 'Trace faulting instructions')
TraceFlag('ExecFetchSeq')
TraceFlag('ExecOpClass')
TraceFlag('ExecRegDelta')
TraceFlag('ExecResult')
TraceFlag('ExecSpeculative')
TraceFlag('ExecSymbol')
TraceFlag('ExecThread')
TraceFlag('ExecTicks')
TraceFlag('ExecMicro')
TraceFlag('ExecMacro')
TraceFlag('Fetch')
TraceFlag('IntrControl')
TraceFlag('PCEvent')
TraceFlag('Quiesce')

CompoundFlag('Exec', [ 'ExecEnable', 'ExecTicks', 'ExecOpClass', 'ExecThread',
    'ExecEffAddr', 'ExecResult', 'ExecSymbol', 'ExecMicro', 'ExecFaulting' ])
CompoundFlag('ExecNoTicks', [ 'ExecEnable', 'ExecOpClass', 'ExecThread',
    'ExecEffAddr', 'ExecResult', 'ExecMicro', 'ExecFaulting' ])
